View AD8124_5402340.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

triple differential receiver with 200 meter adjustable cable equalization AD8124 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features compensates cables to 200 meters for wideband video all resolutions through uxga fast rise and fall times 8 ns with 2 v step @ 200 meters of utp cable 37 db peak gain at 100 mhz two frequency response gain adjustment pins high frequency peaking adjustment (v peak ) broadband flat gain adjustment (v gain ) pole location adjustment pin (v pole ) compensates for variations between cables can be optimized for either utp or coaxial cable dc output offset adjust (v offset ) low output offset voltage: 24 mv compensates both rgb and ypbpr two on-chip comparators with hysteresis can be used for common-mode sync extraction available in 40-lead, 6 mm 6 mm lfcsp applications keyboard-video-mouse (kvm) digital signage rgb video over utp cables professional video projection and distribution hd video security video functional block diagram out r +in r ?in r AD8124 out g +in g ?in g out b +in b ? in b ?in cmp1 +in cmp1 ?in cmp2 +in cmp2 out cmp2 out cmp1 v peak v pole v offset v gain 09601-001 figure 1. general description the AD8124 is a triple, high speed, differential receiver and equalizer that compensates for the transmission losses of utp and coaxial cables up to 200 meters in length. various gain stages are summed together to best approximate the inverse frequency response of the cable. logic circuitry inside the AD8124 controls the gain functions of the individual stages so that the lowest noise can be achieved at short-to-medium cable lengths. this technique optimizes its performance for low noise, short-to- medium range applications, while at the same time provides the high gain bandwidth required for longer cable equalization (up to 200 meters). each chan nel features a high impedance differential input that is ideal for interfacing directly with the cable. the AD8124 has three control pins for optimal cable compensation, as well as an output offset adjust pin. two voltage-controlled pins are used to compensate for different cable lengths; the v peak pin controls the amount of high frequency peaking and the v gain pin adjusts the broadband flat gain, which compensates for the low frequency flat cable loss. for added flexibility, an optional pole adjustment pin, v pole , allows movement of the pole locations, allowing for the compensation of different gauges and types of cable as well as variations between different cables and/or equalizers. the v offset pin allows the dc voltage at the output to be adjusted, adding flexibility for dc-coupled systems. the AD8124 is available in a 6 mm 6 mm, 40-lead lfcsp and is rated to operate over the extended temperature range of ?40c to +85c.
AD8124 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? thermal resistance ...................................................................... 5 ? maximum power dissipation ..................................................... 5 ? esd caution.................................................................................. 5 ? pin configuration and function description .............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 10 ? input common-mode voltage range considerations ......... 10 ? applications information .............................................................. 11 ? basic operation .......................................................................... 11 ? comparators ............................................................................... 11 ? sync pulse extraction using comparators............................. 12 ? using the v peak , v pole , v gain , and v offset inputs ................... 12 ? using the AD8124 with coaxial cable.................................... 13 ? driving 75 video cable with the AD8124.......................... 13 ? driving a capacitive load......................................................... 13 ? power supply filtering............................................................... 13 ? layout and power supply decoupling considerations......... 14 ? power-down ............................................................................... 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 1/11revision 0: initial version
AD8124 rev. 0 | page 3 of 16 specifications t a = 25c, v s = 5 v, r l = 150 , belden cable (bl-7987r), v offset = 0 v, v peak , v gain , and v pole are set to recommended settings shown in figure 16 , unless otherwise noted. table 1. parameter test conditions/comments in tp a unit dynamic performance 10% to 90% rise/fall time v out = 2 v step, 200 meters cat-5 8 ns settling time to 2% v out = 2 v step, 200 meters cat-5 47 ns C3 db large signal bandwidth v out = 2 v p-p, <10 meters cat-5 110 mhz v out = 2 v p-p, 200 meters cat-5 52 mhz integrated output voltage noise 200 meter setting, integrated to 160 mhz 4 mv rms input dc performance input voltage range ?in and +in 3.0 v maximum differential voltage swing 4 v p-p voltage gain v o /v i , v gain set for 0 meters of cable 1 v/v common-mode rejection ratio (cmrr) at dc, v peak = v gain = v pole = 0 v ?86 db at dc, v peak = 1.15 v, v gain = 1.4 v, v pole = 1.5 v ?65 db at 1 mhz, v peak = 1.15 v, v gain = 1.4 v, v pole = 1.5 v ?50 db input resistance common mode 4.4 m differential 3.7 m input capacitance common mode 1.0 pf differential 0.5 pf input bias current 2.4 a v offset pin current 30 a v gain pin current 0.5 a v peak pin current 0.4 a v pole pin current 0.4 a adjustment pins v peak input voltage range relative to gnd 0 to 1.5 v v pole input voltage range relative to gnd 0 to 1.5 v v gain input voltage range relative to gnd 0 to 1.5 v v offset to out gain out/v offset , range limited by output swing 1 v/v maximum flat gain v gain = 1.5 v 1.9 db output characteristics output voltage swing 150 load ?3.75 to +3.69 v 1 k load ?3.66 to +3.69 v output offset voltage referred to output, v peak = v gain = v pole = 0 v 24 mv referred to output, v peak = 1.15 v, v gain = 1.4 v, v pole = 1.5 v 37 mv output offset voltage drift referred to output 33 v/c power supply operating voltage range 4.5 5.5 v positive quiescent supply current 132 ma negative quiescent supply current 126 ma supply current drift, i cc /i ee 80 a/c positive power supply rejection ratio dc, referred to output ?51 db negative power supply rejection ratio dc, referred to output ?63 db power down, v ih (minimum) minimum logic 1 voltage 1.1 v power down, v il (maximum) maximum logic 0 voltage 0.8 v positive supply current, powered down v peak = v gain = v pole = 0 v 1.1 a negative supply current, powered down v peak = v gain = v pole = 0 v 0.7 a
AD8124 rev. 0 | page 4 of 16 parameter test conditions/comments min typ max unit comparators output voltage levels v oh /v ol 3.33/0.043 v hysteresis v hyst 70 mv propagation delay t pd, lh /t pd, hl 17.5/10.0 ns rise/fall times t rise /t fall 9.3/9.3 ns output resistance 0.03 operating temperature range ?40 +85 c
AD8124 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltage 11 v power dissipation see figure 2 input voltage (any input) v s? ? 0.3 v to v s+ + 0.3 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions; that is, ja is specified for the device soldered in a circuit board in still air. table 3. thermal resistance with the underside pad connected to the plane package type/pcb type ja unit 40-lead lfcsp/4-layer 29 c/w maximum power dissipation the maximum safe power dissipation in the AD8124 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8124. exceeding a junction temperature of 175c for an extended time can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipation due to each load current is calculated by multiplying the load current by the voltage difference between the associated power supply and the output voltage. the total power dissipation due to load currents is then obtained by taking the sum of the individual power dissipations. rms output voltages must be used when dealing with ac signals. airflow reduces ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a solid plane (usually the ground plane) to achieve the specified ja . figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 40-lead lfcsp (29c/w) on a jedec standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a pcb plane. ja values are approximations. 0 ?40 ?20 0 20 40 60 80 ambient temperature (c) maximum power dissipation (w) 1 2 3 4 5 6 7 09601-003 figure 2. maximum power dissipation vs. temperature for a 4-layer board esd caution
AD8124 rev. 0 | page 6 of 16 pin configuration and function description 1 nc gnd +in cmp1 out cmp1 v s+ _cmp v s? v s+ v s? v offset gnd v pole v peak v gain v s+ ?in g +in b ?in b ?in cmp1 out cmp2 ?in cmp2 +in cmp2 nc out b out g out r v s? v s+ v s? v s+ v s? v s+ nc v s? _cmp nc pd nc +in r +in g nc 1 2 3 4 5 6 7 8 9 10 23 24 25 26 27 28 29 30 22 21 1 1 1 2 1 3 1 5 1 7 1 6 1 8 1 9 2 0 1 4 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 3 2 3 1 top view (not to scale) AD8124 ?in r 2 nc = no connect notes 1. exposed paddle on the bottom of the package must be connected to a pcb plane to achieve specified thermal resistance. 09601-004 figure 3. pin configuration table 4. pin function descriptions pin o. nemonic description 1, 10, 20, 21, 30, 40 nc no internal connection. 2 +in cmp1 positive input, comparator 1. 3 ?in cmp1 negative input, comparator 1. 4 out cmp1 output, comparator 1. 5 v s+ _cmp positive power supply, comparator. must be connected to v s+ . 6 out cmp2 output, comparator 2. 7 ?in cmp2 negative input, comparator 2. 8 +in cmp2 positive input, comparator 2. 9 v s? _cmp negative power supply, comparator. must be connected to v s? . 11, 14, 17, 22, 33 v s? negative power supply, equalizer sections. 12 out b output, blue channel. 13, 16, 19, 29, 36 v s+ positive power supply, equalizer sections. 15 out g output, green channel. 18 out r output, red channel. 23 v offset output offset control voltage. 24, 39 gnd signal ground reference. 25 v gain broadband flat gain control voltage. 26 v peak equalizer high frequency boost control voltage. 27 v pole equalizer pole location adjustment control voltage. 28 pd power down. 31 +in r positive input, red channel. 32 ?in r negative input, red channel. 34 +in g positive input, green channel. 35 ?in g negative input, green channel. 37 +in b positive input, blue channel. 38 ?in b negative input, blue channel. exposed underside pad thermal plane connection. connect to any pcb plane with voltage between v s+ and v s? .
AD8124 rev. 0 | page 7 of 16 typical performance characteristics t a = 25c, v s = 5 v, r l = 150 , belden cable (bl-7987r), v offset = 0 v, v peak , v gain , and v pole are set to recommended settings shown in figure 16 , unless otherwise noted. 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 100k 1m 10m 100m 1g gain (db) frequency (hz) 09601-033 v peak = 0v v pole = 0v v o = 1v p-p v gain = 0v v gain = 0.6v v gain = 1.5v 3 0 ?3 ?6 ?9 ?12 100k 1m 10m 100m gain (db) frequency (hz) 09601-007 v o = 2v p-p 50m 100m 150m 200m figure 4. frequency response for various v gain without cable figure 7. equalized frequency response for various cable lengths 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 100k 1m 10m 100m gain (db) frequency (hz) 09601-005 v peak = 0v v peak = 1.5v v gain = 0.6v v pole = 1.5v v o = 1v p-p 120 100 80 60 40 20 0 25 50 75 100 125 150 175 200 bandwidth (mhz) cable length (meters) 09601-008 v out = 2v p-p figure 5. frequency response for various v peak without cable figure 8. equalized ?3 db bandwidth vs. cable length ?6 ?4 ?2 0 2 4 6 0 50 100 150 200 250 300 350 400 450 500 vol t age (v) time (ns) input output v gain = 0.6v v peak = 0v v pole = 0v 09601-009 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 100k 1m 10m 100m gain (db) frequency (hz) 09601-006 v pole = 0v v pole = 1.5v v gain = 0.6v v peak = 1.5v v o = 1v p-p figure 6. frequency response for various v pole without cable figure 9. overdrive recovery
AD8124 rev. 0 | page 8 of 16 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 50 100 150 200 250 300 350 400 450 500 output voltage (v) time (ns) 09601-010 50m 200m figure 10. pulse response for various cable lengths (2 mhz) 1000 100 0 100k 1m 10m 100m output voltage noise (nv/ hz) frequency (hz) 09601-011 0m 200m figure 11. output voltage noise vs. frequency for various cable lengths ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 0.1 1 10 100 cmrr (db) frequency (mhz) v gain = 0v, v peak = 0v, v pole = 0v v gain = 1.4v, v peak = 1.15v, v pole = 1.5v 09601-012 figure 12. cmrr vs. frequency 1.5 1.0 0.5 ?0.5 ?1.0 0 ?1.5 024681 output voltage (v) time (s) 09601-013 0 50m 200m figure 13. pulse response for various cable lengths (100 khz) 6 5 4 3 2 1 0 25 50 75 100 125 150 175 200 integrated output voltage noise from 100khz to 160mhz (mvrms) cable length (meters) 09601-014 figure 14. integrated output voltage noise vs. cable lengths 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100k 1m 10m 100m crosstalk (db) frequency (hz) 09601-015 v gain = 0v, v peak = 0v, v pole = 0v v gain = 1.4v, v peak = 1.15v, v pole = 1.5v figure 15. crosstalk vs. frequency
AD8124 rev. 0 | page 9 of 16 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 02 175 150 125 100 755025 control voltage (v) cable length (meters) 09601-016 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 25 50 75 100 125 150 175 200 cable length (meters) control voltage (v) v peak v pole v gain 09601-017 v peak v pole v gain figure 16. recommended settings for utp cable figure 17. recommended settings for coaxial cable
AD8124 rev. 0 | page 10 of 16 theory of operation the AD8124 is a unity-gain, triple, wideband, low noise analog line equalizer that compensates for losses in utp and coaxial cables up to 200 meters in length. the 3-channel architecture is targeted at high resolution rgb applications but can be used in hd ypbpr applications as well. three continuously adjustable control voltages, common to the rgb channels, are available to the designer to provide compensation for various cable lengths as well as for variations in the cable itself. the v peak input is used to control the amount of high frequency peaking. v peak is the primary control that is used to compensate for frequency and cable-length dependent, high frequency losses that are present due to the skin effect of the cable. a second control pin, v gain , is used to adjust broadband gain to compensate for low frequency flat losses present in the cable. a third control, v pole , is used to move the positions of the equalizer poles and can be linearly derived from v peak , as illustrated in the typical performance characteristics and applications information sections, for utp and coaxial cables. finally, an output offset adjust control, v offset , allows the designer to shift the output dc level. the AD8124 has a high impedance differential input that makes termination simple and allows dc-coupled signals to be received directly from the cable. the AD8124 input can also be used in a single-ended fashion in coaxial cable applications. the AD8124 has a low impedance output that is capable of driving a 150 load. for systems where the AD8124 has to drive a high impedance capacitive load, it is recommended that a small series resistor be placed between the output and load to buffer the capacitance. the resistor should not be so large as to reduce the overall bandwidth to an unacceptable level. the AD8124 is designed such that systems that use short-to- medium-length cables do not pay a noise penalty for excess gain that they do not require. the high gain is only available for longer length systems where it is required. this feature is built into the v peak control and is transparent to the user. two comparators are provided on-chip that can be used for sync pulse extraction in systems that use sync-on-common mode encoding. each comparator has very low output impedance and can therefore be used in a source-only cable termination scheme by placing a series resistor equal to the cable characteristic impedance directly on the comparator output. additional details are provided in the applications information section. input common-mode voltage range considerations when using the AD8124 as a receiver, it is important to ensure that its input common-mode voltage stays within the specified range. the received common-mode level is calculated by adding the common-mode level of the driver, the single-ended peak amplitude of the received signal, the amplitude of any sync pulses, and the other induced common-mode signals, such as ground shifts between the driver and the AD8124 and pickup from external sources, such as power lines and fluorescent lights. see the applications information section for more details.
AD8124 rev. 0 | page 11 of 16 applications information basic operation the AD8124 is easy to apply because it contains everything on-chip needed for cable loss compensation. figure 19 shows a basic application circuit (power supplies not shown) with common- mode sync pulse extraction that is compatible with the common- mode sync pulse encoding technique used in the ad8134, ad8142, ad8147 , and ad8148 triple differential drivers. if sync extraction is not required, the terminations can be single 100 resistors, and the comparator inputs can be left floating. in figure 19 , the AD8124 feeds a high impedance input, such as a delay line or crosspoint switch, and the additional gain of two that makes up for double termination loss is not required. comparators in addition to general-purpose applications, the two on-chip comparators can be used to extract video sync pulses from the received common-mode voltages or to receive differential digital information. built-in hysteresis helps to eliminate false triggers from noise. the sync pulse extraction using comparators section describes the sync extraction details. the comparator outputs have nearly 0 output impedance and are designed to drive source-terminated transmission lines. the source termination technique uses a resistor in series with each comparator output such that the sum of the comparator source resistance (0 ) and the series resistor equals the transmission line characteristic impedance. the load end of the transmission line is high impedance. when the signal is launched into the source termination, its initial value is one-half its source value because its amplitude is divided by two in the voltage divider formed by the source termination and the transmission line. at the load, the signal experiences nearly 100% positive reflection due to the high impedance load and is restored to nearly its full value. this technique is commonly used in pcb layouts that involve high speed digital logic. figure 18 shows how to apply the comparators with source termination when driving a 50 transmission line that is high impedance at its receive end. 49.9 ? high-z z 0 = 50 ? 09601-018 figure 18. using a comparator with source termination 18 red blue green cmv red cmv blue cmv AD8124 15 12 6 4 v peak 26 25 27 23 28 v pole v offset v gain hsync out vsync out 32 31 green 35 34 38 37 3 2 7 8 received red video received green video received blue video red video out green video out blue video out analog control inputs power-down control gnd reference 24, 39 pd 1 2 1k ? 1k ? 49.9 ? 49.9 ? 49.9 ? 475 ? 49.9 ? 49.9 ? 49.9 ? 47pf 47pf 09601-019 figure 19. basic application circuit with common-mode sync extraction
AD8124 rev. 0 | page 12 of 16 sync pulse extraction using comparators the AD8124 is useful in many systems that transport computer video signals, which typically comprise red, green, and blue (rgb) video signals and separate horizontal and vertical sync signals. because the sync signals are separate and not embedded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them among the three common-mode voltages of the rgb signals. the ad8134 , ad8142, ad8147 , and ad8148 triple differential drivers are natural complements to the AD8124 because they perform the sync pulse encoding with the necessary circuitry on-chip. the sync encoding equations follow: [ hv k vred cm ?= 2 ] (1) [] (2) v2 2 ?= k vgreen cm [ hv k vblue cm += 2 ] (3) where: red v cm , green v cm , and blue v cm are the transmitted common- mode voltages of the respective color signals. k is an adjustable gain constant that is set by the driver . v and h are the vertical and horizontal sync pulses, defined with a weight of ?1 when the pulses are in their low states and a weight of +1 when they are in their high states. the ad8134 , ad8142, and ad8146/ ad8147 / ad8148 data sheets contain further details regarding the encoding scheme. figure 19 illustrates how the AD8124 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the rgb common-mode voltages by the aforementioned drivers. using the v peak , v pole , v gain , and v offset inputs the v peak input is the main peaking control and is used to compensate for the low-pass roll-off in the cable response. the v pole input is a secondary frequency response shaping control that shifts the positions of the equalizer poles. the v gain input controls the wideband flat gain and is used to compensate for the low frequency cable loss that is nominally flat. the v offset input is used to produce an offset at the AD8124 output. the output offset is equal to the voltage applied to the v offset input, limited by the output swing limits. the v peak and v pole controls can be used independently or they can be coupled to form a single peaking control. while figure 16 and figure 17 show recommended settings vs. cable length, designers may find other combinations that they prefer. these two controls give designers extra freedom, as well as the ability to compensate for different cable types (such as utp and coaxial cable), as opposed to having only a single frequency shaping control. in some cases, as would likely be with automatic control, the v peak control is derived from a low impedance source, such as an op amp. figure 20 shows how to derive v pole from v peak in a utp application according to the recommended curves shown in figure 16 when v peak originates from a low impedance source. clearly, the 5 v supply must be clean to provide a clean v pole voltage. v peak 2 + 0.9v 20 ? 5.11k ? v peak v pole 5v 14k ? 8.25k ? v peak 09601-020 figure 20. deriving v pole from v peak with low-z source for the utp cable the 20 series resistor in the v peak path provides capacitive load buffering for the op amp. this value can be modified, depending on the actual capacitive load. in automatic equalization circuits that place the control voltages inside feedback loops, attention must be paid to the poles produced by the summing resistors and load capacitances. the peaking can also be adjusted by a mechanical or digitally controlled potentiometer. in these cases, if the resistance of the potentiometer is a couple of orders of magnitude lower than the values of the resistors used to develop v pole , its resistance can be ignored. figure 21 shows how to use a 500 potentiometer with the resistor values shown in figure 20 scaled up by a factor of 10. v peak 2 + 0.9v 51.1k ? v peak v pole 5v 5v 140k ? 82.5k ? 750 ? 500 ? 09601-021 figure 21. deriving v pole from v peak with a potentiometer for the utp cable many potentiometers have wide tolerances. if a wide tolerance potentiometer is used, it may be necessary to change the value of the 750 resistor to obtain a full swing for v peak . the v gain input is essentially a contrast control and can be set by adjusting it to produce the correct amplitude of a known test signal (such as a white screen) at the AD8124 output. v gain can also be derived from v peak according to the linear relationships shown in figure 16 and figure 17 . figure 22 shows how to derive v pole and v gain from v peak in a utp application that originates from a low-z source. v peak 2 + 0.9v 20 ? 5.11k ? v peak v pole 5v 14k ? 8.25k ? 5.11k ? v gain 0.89 v peak + 0.38v 5v 60.4k ? 133k ? v peak 09601-022 figure 22. deriving v pole and v gain from v peak with low-z source for the utp cable
AD8124 rev. 0 | page 13 of 16 using the AD8124 with coaxial cable the v pole control allows the AD8124 to be used with other types of cable, including coaxial cable. figure 17 presents the recommended settings for v peak , v pole , and v gain when the AD8124 is used with good quality 75 video cable. figure 23 shows how to derive v pole and v gain from v peak in a coaxial cable application where v peak originates from a low-z source. 20 ? 5.11k ? 20k ? v peak v peak ?5v +5v 24.3k ? 47.5k ? 1.16k ? v gain 1.06 v peak ? 0.62v v pole 0.76 v peak ? 0.41v 10k ? 1.24k ? 09601-023 figure 23. deriving v pole and v gain from v peak with low-z source for the coaxial cable the op amp in the circuit that develops v gain is required to insert the offset of ?0.62 v with a gain from v peak to v gain that is close to unity. a passive offset circuit requires an offset injection voltage that is much larger in magnitude than the available ?5 v supply. clearly, the v gain control voltage can also be developed independently. the AD8124 differential input can accept signals carried over unbalanced cable, as shown in figure 24 , for an unbalanced 75 coaxial cable termination. 09601-030 75 ? input from 75 ? cable AD8124 input stage figure 24. terminating a 75 cable driving 75 video cable with the AD8124 when the rgb outputs must drive a 75 line rather than a high impedance load, an additional gain of two is required to make up for the double termination loss (75 source and load terminations). there are two options available for this. one option is to place the additional gain of 2 at the drive end by using the ad8148 triple differential driver to drive the cable. the ad8148 has a fixed gain of 4 instead of the usual gain of 2 and thereby provides the required additional gain of 2 without having to add additional amplifiers to the signal chain. the ad8148 also contains sync-on-common-mode encoding. if sync-on-common-mode is not required, it can be deactivated on the ad8148 by connecting its sync level input to ground. the other option is to include a triple gain-of-2 buffer, such as the ada4862-3 , on the AD8124 rgb outputs, as shown in figure 25 for one channel (power supplies not shown). the ada4862-3 provides the gain of 2 that compensates for the double- termination loss. one video output from AD8124 one channel of ada4862-3 75 ? 75 ? 500 ? 500 ? z 0 = 75 ? 09601-025 figure 25. using the ada4862-3 on AD8124 outputs driving a capacitive load when driving a high impedance capacitive input, it is necessary to place a small series resistor between each of the three AD8124 video outputs and the load to buffer the input capacitance of the device being driven. clearly, the resistor value must be small enough to preserve the required bandwidth. power supply filtering external power supply filtering between the system power supplies and the AD8124 is recommended in most applications to prevent supply noise from contaminating the received signal as well as to prevent unwanted feedback through the supplies that may cause instability. figure 26 shows that the AD8124 power supply rejection decreases with increasing frequency. these plots are for the lowest control settings and shift upward as the peaking is increased. 09601-026 ?60 ?50 ?40 ?30 ?20 ?10 0 10 +psrr ?psrr 100k 1m 10m 100m frequency (hz) psrr (db) v gain =0v v peak =0v v pole =0v figure 26. psrr vs. frequency
AD8124 rev. 0 | page 14 of 16 layout and power supply decoupling considerations a suitable filter that uses a surface-mount ferrite bead is shown in figure 27 , and its frequency response is shown in figure 28 . because the frequency response was taken using a 50 network analyzer and with only one 0.1 f capacitor on the AD8124 side, the actual amount of rejection provided by the filter in a real-world application is different from that shown in figure 28 . the general shape of the rejection curve, however, matches figure 28 , providing substantially increased overall psrr from approximately 5 mhz to 500 mhz, where it is most needed. one filter is required on each of the two supplies (not one filter per supply pin). standard high speed pcb layout practices should be adhered to when designing with the AD8124. a solid ground plane is required and controlled impedance traces should be used when interconnecting the high speed signals. source termination resistors on all outputs must be placed as close as possible to the output pins. the exposed paddle on the underside of the AD8124 must be connected to a pad that connects to at least one pcb plane. several thermal vias should be used to make the connection between the pad and the plane(s). fair-rite 2743021447 *all AD8124 supply pins are individually decoupled with a 0.1f capacitor. 0.1f 4700pf 4700pf system supply to AD8124* 09601-027 high quality 0.1 f power supply decoupling capacitors should be placed as close as possible to all supply pins. small surface- mount ceramic capacitors should be used, and tantalum capacitors are recommended for bulk supply decoupling. figure 27. power supply filter power-down ?120 ?100 ?80 ?60 ?40 ?20 0 10k 100k 1m 10m 100m frequency (hz) output response (db) 09601-028 the power-down feature is intended to be used to reduce power consumption when a particular device is not in use and does not place the output in a high-z state when asserted. the input logic levels and supply current in power-down mode are presented in the power supply section of table 1 . figure 28. power supply filter freq uency response in a 50 system
AD8124 rev. 0 | page 15 of 16 outline dimensions compliant to jedec standards mo-220-vjjd-2 122107-a 1 40 10 11 29 28 20 19 4.45 4.30 sq 4.15 top view 6.00 bsc sq 5.75 bsc sq coplanarity 0.08 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) pin 1 indicator 0.30 0.23 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom s eating plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 29. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm, very thin quad (cp-40-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD8124acpz ?40c to +85c 40-lead lfcsp_vq cp-40-4 AD8124acpz-r7 ?40c to +85c 40-lead lfcsp_vq cp-40-4 AD8124acpz-rl ?40c to +85c 40-lead lfcsp_vq cp-40-4 1 z = rohs compliant part.
AD8124 rev. 0 | page 16 of 16 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09601-0-1/11(0)

▲Up To Search▲

Price & Availability of AD8124

	To Download AD8124 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .